Tim9/12 Event Generation Register (Timx_Egr); Tim9/12 Capture/Compare Mode Register 1 (Timx_Ccmr1) - ST STM32F412 Reference Manual

General-purpose timers (TIM9 to TIM14)
18.4.5

TIM9/12 event generation register (TIMx_EGR)

Address offset: 0x14
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:7 Reserved, must be kept at reset value.
Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled
Bits 5:3 Reserved, must be kept at reset value.
Bit 2 CC2G: Capture/compare 2 generation
refer to CC1G description
Bit 1 CC1G: Capture/compare 1 generation
This bit is set by software to generate an event, it is automatically cleared by hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
the CC1IF flag is set, the corresponding interrupt is sent if enabled.
If channel CC1 is configured as input:
The current counter value is captured in the TIMx_CCR1 register. The CC1IF flag is set, the
corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was
already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initializes the counter and generates an update of the registers. The prescaler counter
is also cleared and the prescaler ratio is not affected. The counter is cleared.
18.4.6

TIM9/12 capture/compare mode register 1 (TIMx_CCMR1)

Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits in this register have different functions in input and output modes. For a given bit, OCxx
describes its function when the channel is configured in output mode, ICxx describes its
function when the channel is configured in input mode. So one must take care that the same
bit can have different meanings for the input stage and the output stage.
15 14 13
Res. OC2M[2:0]
IC2F[3:0]
rw rw rw
572/1163
12 11 10 9
Res. Res. Res.
12 11 10 9
OC2PE OC2FE
CC2S[1:0]
IC2PSC[1:0]
rw rw rw rw
8 7 6
Res. Res. TG
w
8 7 6
Res. OC1M[2:0]
IC1F[3:0]
rw rw rw
RM0402 Rev 6
5 4 3 2
Res. Res. Res. CC2G
w
5 4 3 2
OC1PE OC1FE
IC1PSC[1:0]
rw rw rw rw
RM0402
1 0
CC1G UG
w w
1 0
CC1S[1:0]
rw rw