Rcc Ahb1 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb1Lpenr) - ST STM32F412 Reference Manual

Reset and clock control (RCC) for STM32F412xx
6.3.15 RCC AHB1 peripheral clock enable in low power mode register
(RCC_AHB1LPENR)
Address offset: 0x50
Reset value: 0x0061 90FF
Access: no wait state, word, half-word and byte access.
31 30 29
Res. Res. Res.
15 14 13
FLITF
Res. Res.
LPEN LPEN
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 DMA2LPEN: DMA2 clock enable during Sleep mode
Set and cleared by software.
0: DMA2 clock disabled during Sleep mode
1: DMA2 clock enabled during Sleep mode
Bit 21 DMA1LPEN: DMA1 clock enable during Sleep mode
Set and cleared by software.
0: DMA1 clock disabled during Sleep mode
1: DMA1 clock enabled during Sleep mode
Bits 20:17 Reserved, must be kept at reset value.
Bit 16 SRAM1LPEN: SRAM1interface clock enable during Sleep mode
Set and cleared by software.
0: SRAM1 interface clock disabled during Sleep mode
1: SRAM1 interface clock enabled during Sleep mode
Bit 15 FLITFLPEN: Flash interface clock enable during Sleep mode
Set and cleared by software.
0: Flash interface clock disabled during Sleep mode
1: Flash interface clock enabled during Sleep mode
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 CRCLPEN: CRC clock enable during Sleep mode
Set and cleared by software.
0: CRC clock disabled during Sleep mode
1: CRC clock enabled during Sleep mode
Bits 11:8 Reserved, must be kept at reset value.
Bit 7 GPIOHLPEN: IO port H clock enable during sleep mode
Set and reset by software.
0: IO port H clock disabled during sleep mode
1: IO port H clock enabled during sleep mode
146/1163
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
CRC
Res. Res. Res.
rw
24 23 22
DMA2
Res. Res.
LPEN
rw
8 7 6
GPIOH GPIOG GPIOF
Res.
LPEN LPEN
rw rw
RM0402 Rev 6
21 20 19 18
DMA1
Res. Res. Res.
LPEN
rw
5 4 3 2
GPIOE GPIOD GPIOC
LPEN
LPEN LPEN LPEN
rw rw rw rw
RM0402
17 16
SRAM1
Res.
LPEN
rw
1 0
GPIOB GPIOA
LPEN LPEN
rw rw