Otg Device In Endpoint X Interrupt Register (Otg_Diepintx) - ST STM32F412 Reference Manual

RM0402

29.15.45 OTG device IN endpoint x interrupt register (OTG_DIEPINTx)

Address offset: 0x908 + 0x20 * x, (x = 0 to 5)
Reset value: 0x0000 0080
This register indicates the status of an endpoint with respect to USB- and AHB-related
events. It is shown in
endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set.
Before the application can read this register, it must first read the device all endpoints
interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x
interrupt register. The application must clear the appropriate bit in this register to clear the
corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. NAK Res.
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Bits 31:14 Reserved, must be kept at reset value.
Bit 13 NAK: NAK input
Bit 12 Reserved, must be kept at reset value.
Bit 11 PKTDRPSTS: Packet dropped status
Bit 10 Reserved, must be kept at reset value.
Bit 9 Reserved, must be kept at reset value.
Bit 8 Reserved, must be kept at reset value.
Bit 7 TXFE: Transmit FIFO empty
Bit 6 INEPNE: IN endpoint NAK effective
Figure 342. The application must read this register when the IN
28 27 26 25
Res. Res. Res.
12 11 10 9
PKTD
Res. Res.
RPSTS
rc_w1
The core generates this interrupt when a NAK is transmitted or received by the device. In
case of isochronous IN endpoints the interrupt gets generated when a zero length packet is
transmitted due to unavailability of data in the Tx FIFO.
This bit indicates to the application that an ISOC OUT packet has been dropped. This bit
does not have an associated mask bit and does not generate an interrupt.
This interrupt is asserted when the Tx FIFO for this endpoint is either half or completely
empty. The half or completely empty status is determined by the Tx FIFO Empty Level bit in
the OTG_GAHBCFG register (TXFELVL bit in OTG_GAHBCFG).
This bit can be cleared when the application clears the IN endpoint NAK by writing to the
CNAK bit in OTG_DIEPCTLx.
This interrupt indicates that the core has sampled the NAK bit set (either by the application
or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application
has taken effect in the core.
This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit
takes priority over a NAK bit.
USB on-the-go full-speed (OTG_FS)
24 23 22
Res. Res. Res.
8 7 6
IN
Res. TXFE
EPNE EPNM
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RM0402 Rev 6
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
IN
ITTXFE TOC Res.
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17 16
Res. Res.
1 0
EP
XFRC
DISD
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