ST STM32F412 Reference Manual page 802

Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit-
Bit 3 ORE: Overrun error
Note: When this bit is set, the RDR register content will not be lost but the shift register will be
Bit 2 NF: Noise detected flag
Note: This bit does not generate interrupt as it appears at the same time as the RXNE bit that
Note: When the line is noise-free, the NF flag can be disabled by programming the ONEBIT
Bit 1 FE: Framing error
Note: This bit does not generate interrupt as it appears at the same time as the RXNE bit that
Bit 0 PE: Parity error
802/1163
This bit is set by hardware when the word currently being received in the shift register is
ready to be transferred into the RDR register while RXNE=1. An interrupt is generated if
RXNEIE=1 in the USART_CR1 register. It is cleared by a software sequence (an read to the
USART_SR register followed by a read to the USART_DR register).
0: No Overrun error
1: Overrun error is detected
overwritten. An interrupt is generated on ORE flag in case of Multi Buffer
communication if the EIE bit is set.
This bit is set by hardware when noise is detected on a received frame. It is cleared by a
software sequence (an read to the USART_SR register followed by a read to the
USART_DR register).
0: No noise is detected
1: Noise is detected
itself generates an interrupting interrupt is generated on NF flag in case of Multi Buffer
communication if the EIE bit is set.
bit to 1 to increase the USART tolerance to deviations (Refer to
receiver tolerance to clock deviation on page
This bit is set by hardware when a de-synchronization, excessive noise or a break character
is detected. It is cleared by a software sequence (an read to the USART_SR register
followed by a read to the USART_DR register).
0: No Framing error is detected
1: Framing error or break character is detected
itself generates an interrupt. If the word currently being transferred causes both frame
error and overrun error, it will be transferred and only the ORE bit will be set.
An interrupt is generated on FE flag in case of Multi Buffer communication if the EIE bit
is set.
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a
software sequence (a read from the status register followed by a read or write access to the
USART_DR data register). The software must wait for the RXNE flag to be set before
clearing the PE bit.
An interrupt is generated if PEIE = 1 in the USART_CR1 register.
0: No parity error
1: Parity error
RM0402 Rev 6
Section 25.4.5: USART
782).