Figure 13. Clock Tree - ST STM32F412 Reference Manual

Reset and clock control (RCC) for STM32F412xx
LSI RC
32 kHz
OSC32_IN
LSE OSC
32.768 kHz
OSC32_OUT
MCO2
MCO2
/1 to 5
MCO1 /1 to 5
MCO1
HSI RC
16 MHz
OSC_OUT
4-26 MHz
HSE OSC
OSC_IN
PLLM
/2 to 63
/P
VCO
/Q
xN
/R
PLL
/P
VCO
/Q
xN
/R
PLLI2S
PLLI2SM
/2 to 63
I2S_CKIN
1. For full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in
the device datasheet.
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Figure 13. Clock tree

Enable
LSI watchdog
RTC / AWU
LSE
SYSCLK
HSE_RTC
PLLI2SCLK
HSE
PLLCLK
/2 to 31
LSE
HSI
HSI
HSI
HSE
PLLCLK
HSE
PLLSRC
HSI
HS_ck
PLLCLK
PLLI2SCLK
PLLI2SSRC
HS_ck
IWDGCLK
RTC / AWU
enable
clock
AHB
PRESC
/1,2,..512
/8
APB1
PRESC
/1,2,4,8,16
If (APB1 presc = 1) x1
APB2
PRESC
/1,2,4,8,16
SW
If (APB2 presc = 1) x1
SYSCLK
CK48MSEL
PLL48CK
I2S1RC
HS_ck
R1
R2
I2S_CKIN
I2S2RC
HS_ck
R1
R2
I2S_CKIN
N multiplier range: 50 to 432
Q divider range: 2 to 15
R divider range: 2 to 7
P divider options: 2, 4, 6, 8
RM0402 Rev 6
Not (sleep or deep sleep)
Not deepsleep
Peripheral
clock enable
Clock enable
Peripheral
clock enable
Peripheral
clock enable
else x2
Peripheral
clock enable
Peripheral
clock enable
else x2
CKDFSDMSEL
DFSDM_ck_enable
CKSDIOSEL
SDIO_ck_enable
USB_ck_enable
RNG_ck_enable
I2S_ck_enable1
I2S_ck_enable2
CKDFSDAMSEL
CKDFSDM_ck_enable
I2C4SEL
I2C4_ck_enable
HSI
SYSCLK
ck_APB1
RM0402
CPU clock
FCLK Cortex
free-running clock
AHB peripheral
clocks
SysTick
clock
AHB1 peripheral
clocks
APB1 timer
clocks
APB2 peripheral
clocks
APB2 timer
clocks
CK_DFSDM
SDIO
USB FS
RNG
I2S clock
For IPs on APB1
I2S clock
For IPs on APB2
CK_DFSDM_Audio
I2C4 clock
Clock for I2C FM+
MSv39615V2