Otg Device In Endpoint X Transfer Size Register (Otg_Dieptsizx) - ST STM32F412 Reference Manual

USB on-the-go full-speed (OTG_FS)

29.15.48 OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx)

Address offset: 0x910 + 0x20 * x, (x = 1 to 5)
Reset value: 0x0000 0000
The application must modify this register before enabling the endpoint. Once the endpoint is
enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in
OTG_DIEPCTLx), the core modifies this register. The application can only read this register
once the core has cleared the endpoint enable bit.
31 30 29
Res. MCNT[1:0]
rw rw
15 14 13
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Bit 31 Reserved, must be kept at reset value.
Bits 30:29 MCNT[1:0]: Multi count
Bits 28:19 PKTCNT[9:0]: Packet count
Bits 18:0 XFRSIZ[18:0]: Transfer size
1054/1163
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
For periodic IN endpoints, this field indicates the number of packets that must be transmitted
per frame on the USB. The core uses this field to calculate the data PID for isochronous IN
endpoints.
01: 1 packet
10: 2 packets
11: 3 packets
Indicates the total number of USB packets that constitute the transfer size amount of data for
this endpoint.
This field is decremented every time a packet (maximum size or short packet) is read from
the Tx FIFO.
This field contains the transfer size in bytes for the current endpoint. The core only interrupts
the application after it has exhausted the transfer size amount of data. The transfer size can
be set to the maximum packet size of the endpoint, to be interrupted at the end of each
packet.
The core decrements this field every time a packet from the external memory is written to the
Tx FIFO.
24 23 22
PKTCNT[9:0]
rw rw rw
8 7 6
XFRSIZ[15:0]
rw rw rw
RM0402 Rev 6
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
RM0402
17 16
XFRSIZ[18:16]
rw rw
1 0
rw rw