Flexible static memory controller (FSMC)
Mode D - asynchronous access with extended address
266/1163
Figure 42. Mode D read access waveforms
A[25:0]
NADV
NEx
NOE
NWE
High
D[15:0]
ADDSET
HCLK cycles
Figure 43. Mode D write access waveforms
Memory transaction
ADDHLD
HCLK cycles
RM0402 Rev 6
data driven
by memory
DATAST
HCLK cycles
RM0402
MS34486V1
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