Supported Memories And Transactions; Table 48. 16-Bit Multiplexed I/O Psram - ST STM32F412 Reference Manual

RM0402
FSMC signal
name
NE[x]
NOE
NWE
NL(= NADV)
NWAIT
NBL[1:0]
The maximum capacity is 512 Mbits.
PSRAM, 16-bit multiplexed I/Os
FSMC signal
name
CLK
A[25:16]
AD[15:0]
NE[x]
NOE
NWE
NL(= NADV)
NWAIT
NBL[1:0]
The maximum capacity is 512 Mbits (26 address lines).
11.6.2

Supported memories and transactions

Table 49
transactions when the memory data bus is 16-bit wide for NOR Flash memory, PSRAM and
SRAM. The transactions not allowed (or not supported) by the FSMC are shown in gray in
this example.
Table 47. Non-multiplexed I/Os PSRAM/SRAM (continued)
I/O
O Chip select, x = 1..4 (called NCE by PSRAM (CellularRAM™ i.e. CRAM))
O
O
O Address valid only for PSRAM input (memory signal name: NADV)
I
O Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)

Table 48. 16-Bit multiplexed I/O PSRAM

I/O
O
O
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
I/O
O Chip select, x = 1..4 (called NCE by PSRAM (CellularRAM™ i.e. CRAM))
O
O
O
I
O Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)
below shows an example of the supported devices, access modes and
Flexible static memory controller (FSMC)
Output enable
Write enable
PSRAM wait input signal to the FSMC
Clock (for synchronous access)
Address bus
A[15:0] and data D[15:0] are multiplexed on the databus)
Output enable
Write enable
Address valid PSRAM input (memory signal name: NADV)
PSRAM wait input signal to the FSMC
RM0402 Rev 6
Function
Function
253/1163
287