Table 66. Fsmc_Bcrx Bitfields (Synchronous Multiplexed Read Mode); Figure 49. Synchronous Multiplexed Read Mode Waveforms - Nor, Psram (Cram) - ST STM32F412 Reference Manual

RM0402

Figure 49. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM)

HCLK
CLK
A[25:16]
NEx
NOE
High
NWE
NADV
NWAIT
(WAITCFG=
0)
A/D[15:0]
1. Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM)
access, they are held low.

Table 66. FSMC_BCRx bitfields (Synchronous multiplexed read mode)

Bit number
31:22
21
20
19
18:16
15
14
13
12
11
10
Memory transaction = burst of 4 half words
addr[25:16]
(DATLAT + 2)
CLK cycles
Addr[15:0]
1 clock 1 clock
cycle cycle
Bit name
Reserved 0x000
WFDIS As needed
CCLKEN As needed
CBURSTRW No effect on synchronous read
CPSIZE 0x0 (no effect in Asynchronous mode)
ASYNCWAIT 0x0
EXTMOD 0x0
To be set to 1 if the memory supports this feature, to be kept at 0
WAITEN
otherwise
WREN No effect on synchronous read
WAITCFG To be set according to memory
Reserved 0x0
Flexible static memory controller (FSMC)
inserted wait state
data data
Data strobes
RM0402 Rev 6
data data
Data strobes
Value to set
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