Hse Clock - ST STM32F412 Reference Manual

RM0402
The clock controller provides a high degree of flexibility to the application in the choice of the
external crystal or the oscillator to run the core and peripherals at the highest frequency
and, guarantee the appropriate frequency for peripherals that need a specific clock like USB
OTG FS, I2S and SDIO.
Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2)
and the low-speed APB (APB1) domains. The maximum frequency of the AHB domain is
100 MHz. The maximum allowed frequency of the high-speed APB2 domain is 100 MHz.
The maximum allowed frequency of the low-speed APB1 domain is 50 MHz
All peripheral clocks are derived from the system clock (SYSCLK) except for:
•
The USB OTG FS clock (48 MHz) and the SDIO clock (
from a specific output of PLL (PLL48CLK)
•
The I2S clock
To achieve high-quality audio performance, the I2S clock can be derived either from a
specific PLL (PLLI2S) or from an external clock mapped on the I2S_CKIN pin. For
more information about I2S clock frequency and precision, refer to
Clock
•
I2CFMP1 clock which can also be generated from HSI, SYSCLK or APB1 clock.
The RCC feeds the external clock of the Cortex System Timer (SysTick) with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock
(HCLK), configurable in the SysTick control and status register.
The timer clock frequencies are automatically set by hardware. There are two cases
depending on the value of TIMPRE bit in RCC_DCKCFGR register:
•
If TIMPRE bit is reset:
If the APB prescaler is configured to a division factor of 1, the timer clock frequencies
(TIMxCLK) are set to HCLK. Otherwise, the timer clock frequencies are twice the
frequency of the APB domain to which the timers are connected: TIMxCLK = 2xPCLKx.
•
If TIMPRE bit is set:
If the APB prescaler is configured to a division factor of 1 or 2, the timer clock
frequencies (TIMxCLK) are set to HCLK. Otherwise, the timer clock frequencies is four
times the frequency of the APB domain to which the timers are connected: TIMxCLK =
4xPCLKx.
FCLK acts as Cortex
®
Cortex -M4 with FPU technical reference manual.
6.2.1

HSE clock

The high speed external clock signal (HSE) can be generated from two possible clock
sources:
•
HSE external crystal/ceramic resonator
• HSE external user clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
generator.
®
-M4 with FPU free-running clock. For more details, refer to the
Reset and clock control (RCC) for STM32F412xx
RM0402 Rev 6
48 MHz) which are coming
≤
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