Table 203. Device-Mode Control And Status Registers - ST STM32F412 Reference Manual

USB on-the-go full-speed (OTG_FS)
Table 202. Host-mode control and status registers (CSRs) (continued)
Acronym
OTG_HPRT
OTG_HCCHARx
OTG_HCINTx
OTG_HCINTMSKx
OTG_HCTSIZx
Device-mode CSR map
These registers must be programmed every time the core changes to device mode.
Acronym
OTG_DCFG
OTG_DCTL
OTG_DSTS
OTG_DIEPMSK
OTG_DOEPMSK
OTG_DAINT
OTG_DAINTMSK
OTG_DVBUSDIS
OTG_DVBUSPULSE
994/1163
Offset
address
0x440 Section 29.15.27: OTG host port control and status register (OTG_HPRT)
0x500
0x520
Section 29.15.28: OTG host channel x characteristics register
(OTG_HCCHARx)
...
0x660
0x508
0x528
Section 29.15.29: OTG host channel x interrupt register (OTG_HCINTx)
....
0x668
0x50C
0x52C
Section 29.15.30: OTG host channel x interrupt mask register
(OTG_HCINTMSKx)
....
0x66C
0x510
0x530
Section 29.15.31: OTG host channel x transfer size register
(OTG_HCTSIZx)
....
0x670

Table 203. Device-mode control and status registers

Offset
address
0x800 Section 29.15.33: OTG device configuration register (OTG_DCFG)
0x804 Section 29.15.34: OTG device control register (OTG_DCTL)
0x808 Section 29.15.35: OTG device status register (OTG_DSTS)
Section 29.15.36: OTG device IN endpoint common interrupt mask
0x810
register (OTG_DIEPMSK)
Section 29.15.37: OTG device OUT endpoint common interrupt mask
0x814
register (OTG_DOEPMSK)
Section 29.15.38: OTG device all endpoints interrupt register
0x818
(OTG_DAINT)
Section 29.15.39: OTG all endpoints interrupt mask register
0x81C
(OTG_DAINTMSK)
Section 29.15.40: OTG device V
0x828
(OTG_DVBUSDIS)
Section 29.15.41: OTG device V
0x82C
(OTG_DVBUSPULSE)
Register name
Register name
RM0402 Rev 6
discharge time register
BUS
pulsing time register
BUS
RM0402