Otg_Fs Registers; Table 204. Data Fifo (Dfifo) Access Register Map; Table 205. Power And Clock Gating Control And Status Registers - ST STM32F412 Reference Manual

USB on-the-go full-speed (OTG_FS)
Data FIFO (DFIFO) access register map
These registers, available in both host and device modes, are used to read or write the FIFO
space for a specific endpoint or a channel, in a given direction. If a host channel is of type
IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the
FIFO can only be written on the channel.
Device IN endpoint 0/Host OUT Channel 0: DFIFO write access
Device OUT endpoint 0/Host IN Channel 0: DFIFO read access
Device IN endpoint 1/Host OUT Channel 1: DFIFO write access
Device OUT endpoint 1/Host IN Channel 1: DFIFO read access
...
Device IN endpoint x
Device OUT endpoint x
1. Where x is 5in device mode and 11 in host mode.
Power and clock gating CSR map
There is a single register for power and clock gating. It is available in both host and device
modes.
Acronym
OTG_PCGCCTL
29.15

OTG_FS registers

These registers are available in both host and device modes, and do not need to be
reprogrammed when switching between these modes.
Bit values in the register descriptions are expressed in binary unless otherwise specified.
996/1163

Table 204. Data FIFO (DFIFO) access register map

FIFO access register section
(1)
/Host OUT Channel x
(1)
/Host IN Channel x

Table 205. Power and clock gating control and status registers

Offset address
0xE00–0xE04
RM0402 Rev 6
(1)
: DFIFO write access
(1)
: DFIFO read access
Register name
Section 29.15.54: OTG power and clock gating control
register (OTG_PCGCCTL)
RM0402
Offset address Access
w
0x1000–0x1FFC
r
w
0x2000–0x2FFC
r
... ...
w
0xX000–0xXFFC
r