Otg Host Channel X Transfer Size Register (Otg_Hctsizx) - ST STM32F412 Reference Manual

USB on-the-go full-speed (OTG_FS)
Bit 8 BBERRM: Babble error mask.
0: Masked interrupt
1: Unmasked interrupt
Bit 7 TXERRM: Transaction error mask.
0: Masked interrupt
1: Unmasked interrupt
Bit 6 Reserved, must be kept at reset value.
Bit 5 ACKM: ACK response received/transmitted interrupt mask.
0: Masked interrupt
1: Unmasked interrupt
Bit 4 NAKM: NAK response received interrupt mask.
0: Masked interrupt
1: Unmasked interrupt
Bit 3 STALLM: STALL response received interrupt mask.
0: Masked interrupt
1: Unmasked interrupt
Bit 2 Reserved, must be kept at reset value.
Bit 1 CHHM: Channel halted mask
0: Masked interrupt
1: Unmasked interrupt
Bit 0 XFRCM: Transfer completed mask
0: Masked interrupt
1: Unmasked interrupt

29.15.31 OTG host channel x transfer size register (OTG_HCTSIZx)

Address offset: 0x510 + 0x20 * x, (x = 0 to 11)
Reset value: 0x0000 0000
31 30 29
DO
DPID[1:0]
PNG
rw
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15 14 13
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1036/1163
28 27 26 25
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12 11 10 9
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24 23 22
PKTCNT[9:0]
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8 7 6
XFRSIZ[15:0]
rw rw rw
RM0402 Rev 6
21 20 19 18
rw rw rw rw
5 4 3 2
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RM0402
17 16
XFRSIZ[18:16]
rw rw
1 0
rw rw