Syscfg Configuration Register (Syscfg_Cfgr) - ST STM32F412 Reference Manual

Advanced arm-based 32-bit mcus

Table of Contents

SYSCFG configuration register (SYSCFG_CFGR)

Address offset: 0x2C

Reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 I2CFMP1_SDA

Bit 0 I2CFMP1_SCL

Set and cleared by software. When this bit is set, it forces FM+ drive capability on

I2CFMP1_SDA pin selected through GPIO port mode register and GPIO alternate

function selection bits.

Set and cleared by software. When this bit is set, it forces FM+ drive capability on

I2CFMP1_SCL pin selected through GPIO port mode register and GPIO alternate

function selection bits.

RM0402 Rev 6

System configuration controller (SYSCFG)

I2CFMP1_SDA I2CFMP1_SCL

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