I 2 S Error Flags - ST STM32F412 Reference Manual

Serial peripheral interface/ inter-IC sound (SPI/I2S)
The BSY flag is cleared:
•
When a transfer completes (except in master transmit mode, in which the
communication is supposed to be continuous)
•
When the I
When communication is continuous:
•
In master transmit mode, the BSY flag is kept high during all the transfers
•
In slave mode, the BSY flag goes low for one I
Note: Do not use the BSY flag to handle each data transmission or reception. It is better to use the
TXE and RXNE flags instead.
Tx buffer empty flag (TXE)
When set, this flag indicates that the Tx buffer is empty and the next data to be transmitted
can then be loaded into it. The TXE flag is reset when the Tx buffer already contains data to
be transmitted. It is also reset when the I
RX buffer not empty (RXNE)
When set, this flag indicates that there are valid received data in the RX Buffer. It is reset
when SPIx_DR register is read.
Channel Side flag (CHSIDE)
In transmission mode, this flag is refreshed when TXE goes high. It indicates the channel
side to which the data to transfer on SD has to belong. In case of an underrun error event in
slave transmission mode, this flag is not reliable and I
switched on before resuming the communication.
In reception mode, this flag is refreshed when data are received into SPIx_DR. It indicates
from which channel side data have been received. Note that in case of error (like OVR) this
flag becomes meaningless and the I
(with configuration if it needs changing).
This flag has no meaning in the PCM standard (for both Short and Long frame modes).
When the OVR or UDR flag in the SPIx_SR is set and the ERRIE bit in SPIx_CR2 is also
set, an interrupt is generated. This interrupt can be cleared by reading the SPIx_SR status
register (once the interrupt source has been cleared).
2
26.6.8 I S error flags
There are three error flags for the I
Underrun flag (UDR)
In slave transmission mode this flag is set when the first clock for data transmission appears
while the software has not yet loaded any value into SPIx_DR. It is available when the
I2SMOD bit in the SPIx_I2SCFGR register is set. An interrupt may be generated if the
ERRIE bit in the SPIx_CR2 register is set.
The UDR bit is cleared by a read operation on the SPIx_SR register.
850/1163
2
S is disabled
2
2
S cell.
RM0402 Rev 6
2
S clock cycle between each transfer
2
S is disabled (I2SE bit is reset).
2
S needs to be switched off and
S should be reset by disabling and then enabling it
RM0402