RM0402
Bit 11 TERR1
This bit is set when the previous TX failed due to an error.
Bit 10 ALST1
This bit is set when the previous TX failed due to an arbitration lost.
Bit 9 TXOK1
The hardware updates this bit after each transmission attempt.
0: The previous transmission failed
1: The previous transmission was successful
This bit is set by hardware when the transmission request on mailbox 1 has been completed
successfully. Refer to
Bit 8 RQCP1
Set by hardware when the last request (transmit or abort) has been performed.
Cleared by software writing a "1" or by hardware on transmission request (TXRQ1 set in
CAN_TI1R register).
Clearing this bit clears all the status bits (TXOK1, ALST1 and TERR1) for Mailbox 1.
Bit 7 ABRQ0
Set by software to abort the transmission request for the corresponding mailbox.
Cleared by hardware when the mailbox becomes empty.
Setting this bit has no effect when the mailbox is not pending for transmission.
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 TERR0
This bit is set when the previous TX failed due to an error.
Bit 2 ALST0
This bit is set when the previous TX failed due to an arbitration lost.
Bit 1 TXOK0
The hardware updates this bit after each transmission attempt.
0: The previous transmission failed
1: The previous transmission was successful
This bit is set by hardware when the transmission request on mailbox 1 has been completed
successfully. Refer to
Bit 0 RQCP0
Set by hardware when the last request (transmit or abort) has been performed.
Cleared by software writing a "1" or by hardware on transmission request (TXRQ0 set in
CAN_TI0R register).
Clearing this bit clears all the status bits (TXOK0, ALST0 and TERR0) for Mailbox 0.
CAN receive FIFO 0 register (CAN_RF0R)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
:
Transmission error of mailbox1
:
Arbitration lost for mailbox1
:
Transmission OK of mailbox1
Figure 324
:
Request completed mailbox1
:
Abort request for mailbox0
:
Transmission error of mailbox0
:
Arbitration lost for mailbox0
:
Transmission OK of mailbox0
Figure 324
:
Request completed mailbox0
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RFOM0 FOVR0 FULL0
RM0402 Rev 6
Controller area network (bxCAN)
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
rs
rc_w1
rc_w1
17
16
Res.
Res.
1
0
FMP0[1:0]
r
r
947/1163
966
Need help?
Do you have a question about the STM32F412 and is the answer not in the manual?
Questions and answers