Quadspi Status Register (Quadspi_Sr) - ST STM32F412 Reference Manual

Advanced arm-based 32-bit mcus

Table of Contents

Quad-SPI interface (QUADSPI)

QUADSPI status register (QUADSPI_SR)

Address offset: 0x0008

Reset value: 0x0000 0000

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:8 FLEVEL[5:0]: FIFO level

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 BUSY: Busy

Bit 4 TOF: Timeout flag

Bit 3 SMF: Status match flag

Bit 2 FTF: FIFO threshold flag

Bit 1 TCF: Transfer complete flag

Bit 0 TEF: Transfer error flag

This field gives the number of valid bytes which are being held in the FIFO. FLEVEL = 0

when the FIFO is empty, and 32 when it is full. In memory-mapped mode and in

automatic status polling mode, FLEVEL is zero.

This bit is set when an operation is on going. This bit clears automatically when the

operation with the Flash memory is finished and the FIFO is empty.

This bit is set when timeout occurs. It is cleared by writing 1 to CTOF.

This bit is set in automatic polling mode when the unmasked received data matches the

corresponding bits in the match register (QUADSPI_PSMAR). It is cleared by writing 1

In indirect mode, this bit is set when the FIFO threshold is reached, or if there is any

data left in the FIFO after reads from the Flash memory are complete. It is cleared

automatically as soon as threshold condition is no longer true.

In automatic polling mode this bit is set every time the status register is read, and the bit

is cleared when the data register is read.

This bit is set in indirect mode when the programmed number of data is transferred or in

any mode when the transfer is aborted.It is cleared by writing 1 to CTCF.

This bit is set in indirect mode when an invalid address is being accessed in indirect

mode. It is cleared by writing 1 to CTEF.

RM0402 Rev 6

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