C Functional Description; Mode Selection; Figure 238. I2C Bus Protocol - ST STM32F412 Reference Manual

RM0402
Note: Some of the above features may not be available in certain products. The user should refer
to the product data sheet, to identify the specific features supported by the I
implementation.
2
24.3 I

C functional description

In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa. The interrupts are enabled or disabled by software. The interface is
connected to the I
with a standard (up to 100 kHz) or fast (up to 400 kHz) I
24.3.1

Mode selection

The interface can operate in one of the four following modes:
•
Slave transmitter
• Slave receiver
•
Master transmitter
• Master receiver
By default, it operates in slave mode. The interface automatically switches from slave to
master, after it generates a START condition and from master to slave, if an arbitration loss
or a Stop generation occurs, allowing multimaster capability.
Communication flow
In Master mode, the I
serial data transfer always begins with a start condition and ends with a stop condition. Both
start and stop conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and
the General Call address. The General Call address detection may be enabled or disabled
by software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is
always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to
Acknowledge may be enabled or disabled by software. The I
addressing 7-bit/ 10-bit and/or general call address) can be selected by software.
2
C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected
2
C interface initiates a data transfer and generates the clock signal. A
Figure 238. I
SDA
MSB
SCL
1
Start
condition
RM0402 Rev 6
Inter-integrated circuit (I
2
C bus.
Figure 238.
2
C bus protocol
2 8
2
C interface addresses (dual
2
C) interface
2
C interface
ACK
9
Stop
condition
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