Dfsdm Filter X Control Register 2 (Dfsdm_Fltxcr2) - ST STM32F412 Reference Manual

Digital filter for sigma delta modulators (DFSDM)
Bit 5 JDMAEN: DMA channel enabled to read data for the injected channel group
0: The DMA channel is not enabled to read injected data
1: The DMA channel is enabled to read injected data
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bit 4 JSCAN: Scanning conversion mode for injected conversions
0: One channel conversion is performed from the injected channel group and next the selected
channel from this group is selected.
1: The series of conversions for the injected group channels is executed, starting over with the
lowest selected channel.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
Bit 3 JSYNC: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger
0: Do not launch an injected conversion synchronously with DFSDM_FLT0
1: Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected
conversion is launched in DFSDM_FLT0 by its JSWSTART trigger
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bit 2 Reserved, must be kept at reset value.
Bit 1 JSWSTART: Start a conversion of the injected group of channels
0: Writing '0' has no effect.
1: Writing '1' makes a request to convert the channels in the injected conversion group, causing
JCIP to become '1' at the same time. If JCIP=1 already, then writing to JSWSTART has no effect.
Writing '1' has no effect if JSYNC=1.
This bit is always read as '0'.
Bit 0 DFEN: DFSDM_FLTx enable
0: DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and
all DFSDM_FLTx functions are stopped.
1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating
according to its setting.
Data which are cleared by setting DFEN=0:
–register DFSDM_FLTxISR is set to the reset state
–register DFSDM_FLTxAWSR is set to the reset state
14.8.2

DFSDM filter x control register 2 (DFSDM_FLTxCR2)

Address offset: 0x104 + 0x80 * x, (x = 0 to 1)
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
384/1163
28 27 26 25
Res. Res. Res.
12 11 10 9
EXCH[3:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
CKAB
Res. SCDIE AWDIE
IE
rw rw
RM0402 Rev 6
21 20 19 18
Res. Res. AWDCH[3:0]
rw rw
5 4 3 2
ROVR JOVR
IE IE
rw rw rw rw
RM0402
17 16
rw rw
1 0
REOC JEOC
IE IE
rw rw