Figure 155. Edge-Aligned Pwm Waveforms (Arr=8) - ST STM32F412 Reference Manual

General-purpose timers (TIM2 to TIM5)
PWM edge-aligned mode
Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to
mode on page
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at '1.
If the compare value is 0 then OCxREF is held at '0.
PWM waveforms in an example where TIMx_ARR=8.
CCRx=4
CCRx=8
CCRx>8
CCRx=0
Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to
mode on page
In PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else
it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in
TIMx_ARR, then ocxref is held at '1. 0% PWM is not possible in this mode.
PWM center-aligned mode
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
'00 (all the remaining configurations having the same effect on the ocxref/OCx signals). The
compare flag is set when the counter counts up, when it counts down or both when it counts
up and down depending on the CMS bits configuration. The direction bit (DIR) in the
506/1163
487.

Figure 155. Edge-aligned PWM waveforms (ARR=8)

0
Counter register
OCXREF
CCxIF
OCXREF
CCxIF
'1'
OCXREF
CCxIF
'0'
OCXREF
CCxIF
490.
Figure 155
1 2 3 4 5
RM0402 Rev 6
Upcounting
shows some edge-aligned
6 7 8 0 1
Downcounting
RM0402
MS31093V1