Software Reset; Figure 211. Fmpi2C Initialization Flowchart - ST STM32F412 Reference Manual

RM0402
23.4.6

Software reset

A software reset can be performed by clearing the PE bit in the FMPI2C_CR1 register. In
that case FMPI2C lines SCL and SDA are released. Internal states machines are reset and
communication control bits, as well as status bits come back to their reset value. The
configuration registers are not impacted.
Here is the list of impacted register bits:
1. FMPI2C_CR2 register: START, STOP, NACK
2. FMPI2C_ISR register: BUSY, TXE, TXIS, RXNE, ADDR, NACKF, TCR, TC, STOPF,
BERR, ARLO, OVR
and in addition when the SMBus feature is supported:
1. FMPI2C_CR2 register: PECBYTE
2. FMPI2C_ISR register: PECERR, TIMEOUT, ALERT
PE must be kept low during at least 3 APB clock cycles in order to perform the software
reset. This is ensured by writing the following software sequence: - Write PE=0 - Check
PE=0 - Write PE=1.
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface

Figure 211. FMPI2C initialization flowchart

Initial settings
Clear PE bit in FMPI2C_CR1
Configure ANFOFF and DNF[3:0] in
FMPI2C_CR1
Configure PRESC[3:0],
SDADEL[3:0], SCLDEL[3:0], SCLH[7:0],
SCLL[7:0] in FMPI2C_TIMINGR
Configure NOSTRETCH in FMPI2C_CR1
Set PE bit in FMPI2C_CR1
End
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