Tim10/11/13/14 Registers; Tim10/11/13/14 Control Register 1 (Timx_Cr1) - ST STM32F412 Reference Manual

RM0402
18.5

TIM10/11/13/14 registers

The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read
accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
18.5.1

TIM10/11/13/14 control register 1 (TIMx_CR1)

Address offset: 0x00
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:8 CKD: Clock division
Bit 7 ARPE: Auto-reload preload enable
Bits 6:3 Reserved, must be kept at reset value.
Bit 2 URS: Update request source
Bit 1 UDIS: Update disable
Bit 0 CEN: Counter enable
12 11 10 9
Res. Res. CKD[1:0]
rw
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (TIx),
00: t = t
DTS CK_INT
01: t = 2 × t
DTS CK_INT
10: t = 4 × t
DTS CK_INT
11: Reserved
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
This bit is set and cleared by software to select the update interrupt (UEV) sources.
0: Any of the following events generate an UEV if enabled:
– Counter overflow
– Setting the UG bit
1: Only counter overflow generates an UEV if enabled.
This bit is set and cleared by software to enable/disable update interrupt (UEV) event
generation.
0: UEV enabled. An UEV is generated by one of the following events:
– Counter overflow
– Setting the UG bit.
Buffered registers are then loaded with their preload values.
1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC,
CCRx). The counter and the prescaler are reinitialized if the UG bit is set.
0: Counter disabled
1: Counter enabled
General-purpose timers (TIM9 to TIM14)
8 7 6
ARPE Res.
rw rw
RM0402 Rev 6
5 4 3 2
Res. Res. Res. URS
rw
1 0
UDIS CEN
rw rw
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