Figure 261. Parity Error Detection Using The 1.5 Stop Bits - ST STM32F412 Reference Manual

Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit-
shifting on the next baud clock edge. In Smartcard mode this transmission is further
delayed by a guaranteed 1/2 baud clock.
•
If a parity error is detected during reception of a frame programmed with a 0.5 or 1.5
stop bit period, the transmit line is pulled low for a baud clock period after the
completion of the receive frame. This is to indicate to the Smartcard that the data
transmitted to USART has not been correctly received. This NACK signal (pulling
transmit line low for 1 baud clock) will cause a framing error on the transmitter side
(configured with 1.5 stop bits). The application can handle re-sending of data according
to the protocol. A parity error is 'NACK'ed by the receiver if the NACK control bit is set,
otherwise a NACK is not transmitted.
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The assertion of the TC flag can be delayed by programming the Guard Time register.
In normal operation, TC is asserted when the transmit shift register is empty and no
further transmit requests are outstanding. In Smartcard mode an empty transmit shift
register triggers the guard time counter to count up to the programmed value in the
Guard Time register. TC is forced low during this time. When the guard time counter
reaches the programmed value TC is asserted high.
•
The de-assertion of TC flag is unaffected by Smartcard mode.
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If a framing error is detected on the transmitter end (due to a NACK from the receiver),
the NACK will not be detected as a start bit by the receive block of the transmitter.
According to the ISO protocol, the duration of the received NACK can be 1 or 2 baud
clock periods.
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On the receiver side, if a parity error is detected and a NACK is transmitted the receiver
will not detect the NACK as a start bit.
Note: A break character is not significant in Smartcard mode. A 0x00 data with a framing error will
be treated as data and not as a break.
No Idle frame is transmitted when toggling the TE bit. The Idle frame (as defined for the
other configurations) is not defined by the ISO protocol.
Figure 261
USART is transmitting a data and is configured with 1.5 stop bits. The receiver part of the
USART is enabled in order to check the integrity of the data and the NACK signal.
The USART can provide a clock to the smartcard through the SCLK output. In smartcard
mode, SCLK is not associated to the communication but is simply derived from the internal
peripheral input clock through a 5-bit prescaler. The division ratio is configured in the
792/1163
details how the NACK signal is sampled by the USART. In this example the

Figure 261. Parity error detection using the 1.5 stop bits

Bit 7 Parity bit
1 bit time
Sampling at
8th, 9th, 10th
Sampling at
8th, 9th, 10th
RM0402 Rev 6
1.5 Stop bit
1.5 bit time
Sampling at
16th, 17th, 18th
0.5 bit
time
Sampling at
8th, 9th, 10th
MS37359V1