Dma Requests - ST STM32F412 Reference Manual

Inter-integrated circuit (I
24.3.8

DMA requests

DMA requests (when enabled) are generated only for data transfer. DMA requests are
generated by Data Register becoming empty in transmission and Data Register becoming
full in reception. The DMA must be initialized and enabled before the I2C data transfer. The
DMAEN bit must be set in the I2C_CR2 register before the ADDR event. In master mode or
in slave mode when clock stretching is enabled, the DMAEN bit can also be set during the
ADDR event, before clearing the ADDR flag. The DMA request must be served before the
end of the current byte transfer. When the number of data transfers which has been
programmed for the corresponding DMA stream is reached, the DMA controller sends an
End of Transfer EOT signal to the I
if enabled:
• Master transmitter: In the interrupt routine after the EOT interrupt, disable DMA
requests then wait for a BTF event before programming the Stop condition.
•
Master receiver
–
–
Transmission using DMA
DMA mode can be enabled for transmission by setting the DMAEN bit in the I2C_CR2
register. Data are loaded from a Memory area configured using the DMA peripheral (refer to
the DMA specification) to the I2C_DR register whenever the TxE bit is set. To map a DMA
stream x for I
sequence:
1. Set the I2C_DR register address in the DMA_SxPAR register. The data are moved to
this address from the memory after each TxE event.
2. Set the memory address in the DMA_SxMA0R register (and in DMA_SxMA1R register
in the case of a bouble buffer mode). The data are loaded into I2C_DR from this
memory after each TxE event.
3. Configure the total number of bytes to be transferred in the DMA_SxNDTR register.
After each TxE event, this value is decremented.
4. Configure the DMA stream priority using the PL[0:1] bits in the DMA_SxCR register
5. Set the DIR bit in the DMA_SxCR register and configure interrupts after half transfer or
full transfer depending on application requirements.
6. Activate the stream by setting the EN bit in the DMA_SxCR register.
When the number of data transfers which has been programmed in the DMA Controller
registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the
2
I C interface and the DMA generates an interrupt, if enabled, on the DMA stream interrupt
vector.
Note: Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for transmission.
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2
C) interface
When the number of bytes to be received is equal to or greater than two, the DMA
controller sends a hardware signal, EOT_1, corresponding to the last but one data
byte (number_of_bytes – 1). If, in the I2C_CR2 register, the LAST bit is set, I
automatically sends a NACK after the next byte following EOT_1. The user can
generate a Stop condition in the DMA Transfer Complete interrupt routine if
enabled.
When a single byte must be received: the NACK must be programmed during EV6
event, i.e. program ACK=0 when ADDR=1, before clearing ADDR flag. Then the
user can program the STOP condition either after clearing ADDR flag, or in the
DMA Transfer Complete interrupt routine.
2
C transmission (where x is the stream number), perform the following
2
C interface and generates a Transfer Complete interrupt
RM0402 Rev 6
RM0402
2
C