Table 20. Stop Operating Modes - ST STM32F412 Reference Manual

Power controller (PWR)
Stop mode
STOP MR
STOP MRFPD
STOP LP
STOP LPFPD
STOP MRLV
STOP LPLV
Entering Stop mode
The Stop mode is entered according to
SLEEPDEEP bit in the Cortex
Refer to
To further reduce power consumption in Stop mode, the internal voltage regulator can be put
in low-power mode. This is configured by the LPDS bit of the
(PWR_CR).
If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory
access is finished.
If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB
access is finished.
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Table 20. Stop operating modes

MRLV bit LPLV bit
0 -
0 -
0 0
- 0
1 -
- 1
®
Table 21 for details on how to enter the Stop mode.
FPDS bit LPDS bit
0 0
1 0
0 1
1 1
- 0
- 1
Section : Entering low-power
-M4 with FPU System Control register is set.
RM0402 Rev 6
Wakeup latency
HSI RC startup time
HSI RC startup time +
Flash wakeup time from Deep
Power Down mode
HSI RC startup time +
regulator wakeup time from LP
mode
HSI RC startup time +
Flash wakeup time from Deep
Power Down mode +
regulator wakeup time from LP
mode
HSI RC startup time +
Flash wakeup time from Deep
Power Down mode +
Main regulator from low voltage
mode
HSI RC startup time +
Flash wakeup time from Deep
Power Down mode +
regulator wakeup time from Low
Voltage LP mode
mode, when the
PWR power control register
RM0402