Embedded Flash Memory Interface; Introduction; Main Features; Figure 3. Flash Memory Interface Connection Inside System Architecture - ST STM32F412 Reference Manual

Embedded Flash memory interface

3 Embedded Flash memory interface
3.1

Introduction

The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms.
The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.
3.2

Main features

•
Flash memory read operations
•
Flash memory program/erase operations
•
Read / write protections
•
Prefetch on I-Code
•
64 cache lines of 128 bits on I-Code
•
8 cache lines of 128 bits on D-Code
Figure 3

Figure 3. Flash memory interface connection inside system architecture

Cortex-M4 with FPU
Cortex
core
58/1163
shows the Flash memory interface connection inside the system architecture.
I-Code
I-Code bus
D-Code
S bus
D-code bus
DMA1
DMA2
Access to instruction in Flash memory
Access to data and literal pool in Flash memory
FLITF register access
AHB
32-bit
instruction
bus
AHB
32-bit
data bus
AHB
32-bit
system bus
RM0402 Rev 6
Flash
memory
Flash interface
bus
128 bits
FLITF registers
RM0402
Flash
memory
AHB
periph1
SRAM and
External
memories
AHB
periph2
MS31423V1