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The timer counters are initialized to H'00 at a reset and in the standby modes.
7.2.2 Time Constant Registers A and B (TCORA and TCORB)—H'FFCA and H'FFCB
(TMR0), H'FFD2 and H'FFD3 (TMR1)
Bit
7
Initial value
1
Read/Write
R/W
TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually
compared with the constants written in these registers. When a match is detected, the
corresponding compare-match flag (CMFA or CMFB) is set in the timer control/status register
(TCSR).
The timer output signal (TMO0 or TMO1) is controlled by these compare-match signals as
specified by output select bits 3 to 0 (OS3 to OS0) in the timer control/status register (TCSR).
TCORA and TCORB are initialized to H'FF at a reset and in the standby modes.
Compare-match is not detected during the T
item (3) in section 7.6, "Application Notes."
7.2.3 Timer Control Register (TCR)—H'FFC8 (TMR0), H'FFD0 (TMR1)
Bit
7
CMIEB CMIEA
Initial value
0
Read/Write
R/W
Each TCR is an 8-bit readable/writable register that selects the clock source and the time at which
the timer counter is cleared, and enables interrupts.
The TCRs are intialized to H'00 at a reset and in the standby modes.
For timing diagrams, see section 7.3, "Operation."
Bit 7-Compare-match Interrupt Enable B (CMIEB): This bit selects whether to request
compare-match interrupt B (CMIB) when compare-match flag B (CMFB) in the timer
control/status register (TCSR) is set to "1".
6
5
4
1
1
1
R/W
R/W
R/W
state of a write cycle to TCORA or TCORB. See
3
6
5
4
OVIE
CCLR1 CCLR0
0
0
0
R/W
R/W
R/W
146
3
2
1
1
1
1
R/W
R/W
R/W
3
2
1
CKS2
CKS1
0
0
0
R/W
R/W
R/W
0
1
R/W
0
CKS0
0
R/W
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