Register Descriptions; Timer Counter V (Tcntv); Time Constant Registers A And B (Tcora, Tcorb) - Hitachi H8/3672 Series Hardware Manual

10.3

Register Descriptions

Time V has the following registers. For details on register addresses and register states during
each process, refer to appendix B, Internal I/O Registers.
• Timer counter V(TCNTV)
• Timer constant register A(TCORA)
• Timer constant register B(TCORB)
• Timer control register V0(TCRV0)
• Timer control/status register V(TCSRV)
• Timer control register V1(TCRV1)
10.3.1

Timer Counter V (TCNTV)

TCNTV is an 8-bit up-counter. The clock source is selected by bits CKS2 to CKS0 in Timer
Control Register V0(TCRV0). The TCNTV value can be read and written by the CPU at any time.
TCNTV can be cleared by an external reset input signal, or by compare match A or B. The
clearing signal is selected by bits CCLR1 and CCLR0 in TCRV0.
When TCNTV overflows, OVF is set to 1 in Timer Control/Status Register V(TCSRV).
TCNTV is initialized to H'00.
10.3.2

Time Constant Registers A and B (TCORA, TCORB)

TCORA and TCORB have the same function.
TCORA and TCORB are 8-bit read/write registers.
TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match,
CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested.
Note that they must not be compared during the T3 state of a TCORA write cycle.
Timer output from the TMOV pin can be controlled by the identifying signal (compare match A)
and the settings of bits OS3 to OS0 in TCSRV.
TCORA is initialized to H'FF.
Rev. 1.0, 03/01, page 111 of 280