Bus Control Register (Bcr) - Hitachi H8/3008 Hardware Manual

Bit 5—Address 21 Enable (A21E): Enables PA
Writing 0 in this bit enables A
modified and PA has its ordinary port functions.
6
Bit 5
A21E
0
1
Bit 4—Address 20 Enable (A20E): Enables PA
written to this bit, PA
address output pin, and in modes 1 and 2, as a normal port pin.
Bit 4
A20E
0
1
Bits 3 to 1—Reserved: These bits cannot be modified and are always read as 1.
Bit 0—Bus Release Enable (BRLE): Enables or disables release of the bus to an external device.
Bit 0
BRLE
0
1
6.2.5

Bus Control Register (BCR)

7
Bit
ICIS1
Initial value 1
Read/Write R/W
Notes: 1. 1 must not be written in bits 5 to 3.
2. 0 must not be written in bit 2.
BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the
area division unit, selects the extended memory map, and enables or disables WAIT pin input.
output from PA
21
Description
PA is the A address output pin
6 21
PA is an input/output pin
6
functions as address output A
7
Description
PA is the A address output pin (In mode 3 or 4)
7 20
PA is an input/output pin (In mode 1 or 2)
7
Description
The bus cannot be released to an external device
BREQ and BACK can be used as input/output pins
The bus can be released to an external device
6 5
ICIS0 —
1 0*
R/W —
to be used as the A
6
. In modes other than 3 and 4, this bit cannot be
6
to be used as an address output pin. When 0 is
7
. In modes 3 and 4, PA
20
4
—
1 1
0*
—
address output pin.
21
functions as an
7
3 2
— —
1 2
0* 1*
— —
(Initial value)
(Initial value)
1 0
RDEA WAITE
1 0
R/W R/W
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