NXP Semiconductors PN7462 series User Manual page 175

NXP Semiconductors
Bit Symbol
2 T2_MODE_SEL
1 T2_RELOAD_ENAB
LE
0 T2_ENABLE
Table 212. CLIF_TIMER0_RELOAD_REG register (address 0084h)
* = reset value
Bit Symbol
31:20 RESERVED
19:0 T0_RELOAD_VALU
E
Table 213. CLIF_TIMER1_RELOAD_REG register (address 0088h)
* = reset value
Bit Symbol
31:20 RESERVED
19:0 T1_RELOAD_VALU
E
Table 214. CLIF_TIMER2_RELOAD_REG register (address 008Ch)
* = reset value
Bit Symbol
31:20 RESERVED
19:0 T2_RELOAD_VALU
E
UM10858
User manual
COMPANY PUBLIC
Access Value
001
010
011
100
101
110
111
R/W 0 – 1
0*
1
R/W 0*, 1
0*
1
R/W 0*, 1
Access Value
R 0
R/W 0000h - FFFFFh Reload value of the timer T0.
00h*
Access Value
R 0
R/W 0000h - FFFFFh Reload value of the timer T1.
00h*
Access Value
R 0
R/W 0000h - FFFFFh Reload value of the timer T2.
00h*
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Description
3.39 MHz counter
1.70 MHz counter
848 kHz counter
424 kHz counter
212 kHz counter
106 kHz counter
53 kHz counter
Configuration of the timer T2 clock.
Prescaler is disabled: the timer frequency matches CLIF
clock frequency (13.56MHz).
Prescaler is enabled: the timer operates on the prescaler
signal frequency (chosen by T2_PRESCALE_SEL).
If set to 0, the timer T2 will stop on expiration.
After expiration, the timer T2 will stop counting, i.e., remain
zero, reset value.
After expiration, the timer T2 will reload its preset value and
continue counting down.
Enables the timer T2
Description
Reserved
reset value
Description
Reserved
reset value
Description
Reserved
reset value
UM10858
© NXP B.V. 2018. All rights reserved.
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