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14.2.7.3 RX CRC
For reception, the CRC is considered as data, and is stored in the memory. Number of
received data is RX_LENGTH, where RX_LENGTH is programmed to Payload_size + 1.
As a result of the reception, the firmware can read back the received CRC byte in
memory (last received byte), and can check in CRC register that CRC_RX_VAL is 0
(CRC xor CRC). This is shown on figure
14.2.8 SPI Register overview
Table 294. SPI master register overview (base address 0x4003 4000)
Name
SPIM_STATUS_REG
SPIM_CONFIG_REG
SPIM_CONTROL_REG
SPIM_RX_BUFFER_REG
SPIM_RX_BUFFER_CRC_REG
SPIM_TX_BUFFER_REG
SPIM_TX_BUFFER_CRC_REG
UM10858
User manual
COMPANY PUBLIC
Fig 55. TX CRC computation with TX_CRC_PAYLOAD_OFFSET=1 and
TX_APPEND_CRC=0
Fig 56. RX CRC computation with RX_CRC_PAYLOAD_OFFSET=1
Address
offset
0000h
0004h
0008h
000Ch
0010h
0014h
0018h
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
Fig
56.
Width
Access
Reset value
(bits)
32
R
00000000h
32
R/W
00000002h
32
W
00000000h
32
R/W
00000000h
32
R/W
000001FFh
32
R/W
00000000h
32
R/W
000201FFh
314514
UM10858
PN7462 family HW user manual
Description
Status
Configuration of SPI Master
RX/TX control
Configuration of RX buffer
Configuration of RX CRC
Configuration of TX buffer
Configuration of TX CRC
© NXP B.V. 2018. All rights reserved.
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