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NXP Semiconductors
1.2.4 Cortex M0 microcontroller
• Processor core
• Memory
• Debug Option
• Master Interfaces:
• Host Interfaces
• Up to 21 General-Purpose I/O (GPIO) with configurable pull-up/pull-down resistors
• GPIOs 1 to 12 can be used as edge and level sensitive interrupt sources
• Power
UM10858
User manual
COMPANY PUBLIC
•
ISO/IEC 14443 Type A and B
•
Support for MIFARE Classic card
•
ISO/IEC 15693 and ISO/IEC 18000-3 mode 3
•
iClass serial number support
•
Low power card detection function
•
Compliance with EMV Contactless protocol specification
•
Compliance with NFC standard
− 32-bit ARM cortex M0 processor
− Built-in Nested Vectored Interrupt Controller (NVIC)
− Non-maskable interrupt
− System Tick Timer 24 bits
− Running frequency up to 20 MHz
− Clock management to enable low power consumption
− Flash: 160 kB
− RAM: 12 kB
− EEPROM: 4 kB
− 40 K boot ROM included, including USB mass storage primary boot loader for
code download.
− Serial Wire Debug interface (SWD)
− SPI half-duplex, up to 6.78 Mbit/s
− I²C supporting fast mode plus, and clock stretching
− HSUART for serial communication, supporting standards speeds from 9600 to
115200 bps, and faster speed up to 1.288 Mbit/s
− SPI half-duplex and full duplex, up to 7 Mbit/s
− I²C Host supporting standard, fast and high-speed mode with multiple address
support
− USB 2.0 full speed, with USB 3.0 hub connection capability
− Two reduced power modes: Sleep mode and hard power down mode
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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