Register Overview And Description - NXP Semiconductors PN7462 series User Manual

NXP Semiconductors
combination of both (depending on the clock settings), is available. This signal can be
overridden using CLIF_PLL_CLK_IN_OK_BYPASS register.
7.3.1 Optimum divider settings for CLIF PLL
Table 50. Optimum divider settings for PLL1 and PLL2
Fin n1 m1
[MHz]
27.12 4 68

7.4 Register overview and description

7.4.1 Clock generator register overview
Table 51. Clock generator register overview (base address 0x4001 0000)
Name
CLKGEN_STATUS_REG
CLKGEN_HFO_XTAL_REG
CLKGEN_HFO_TRIM_REG
CLKGEN_USB_PLL_CONTROL_
REG
CLKGEN_USB_PLL_MDEC_WO_
SOFTDEC_REG
CLKGEN_USB_PLL_NDEC_PDE
C_WO_SOFTDEC_REG
CLKGEN_CLIF_PLL1_CONTROL_
REG
CLKGEN_CLIF_PLL2_CONTROL_
REG
CLKGEN_CLIF_PLL_GLOBAL_C
ONTROL_REG
CLKGEN_INPUT_CLOCK_DETEC
TOR_CONTROL_REG
RESERVED
CLKGEN_CLOCK_PRESENCE_B
YPASS_REG
Unused
UM10858
User manual
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p1 m2 p2
46 44 32.522
Address Width
offset (bits)
0000h 32
0004h 32
0008h 32
000Ch 32
0010h 32
0014h 32
0018h 32
001Ch 32
0020h 32
0024h 32
0028h 32
002Ch 32
0030h - 32
3FFFh
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
Fref1 Fcco1 Fref2
(MHz)
(MHz) (MHz)
13.56 922.1 20.05
Access Reset value
R 00000000h
R/W 00FFF001h
R/W 00000000h
R/W 00F90001h
R/W 00000000h
R/W 00000000h
R/W 02E3B190h
R/W 02E121E0h
R/W 000000C8h
R/W 0000100Dh
R/W 0000000Fh
R/W 00000000h
- -
314514
UM10858
PN7462 family HW user manual
Fcco2 Fpll_clk Fpll_clk
out out2
(MHz)
(MHz) (MHz)
881.99 13.56 27.12
Description
CLKGEN status register
HFO and XTAL control register
HFO trimming value register
PLL Global Control Register
PLL M decoded divider ratio
when the soft decoder is not used
PLL N and P decoded divider
ratio when the soft decoder is not
used
CLIF PLL usage configurations
CLF PLL usage configurations
CLIF PLL integration
configurations
Input clock detector control
Reserved
clock presence for CLIF PLL
unused
© NXP B.V. 2018. All rights reserved.
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