NXP Semiconductors PN7462 series User Manual page 157

NXP Semiconductors
Table 188. CLIF_STATUS_REG register (address 0008h)
* = reset value
Bit Symbol
31 RESERVED
30 DPLL_ENABLE
29 AGC_RFOFF_DET
28 CRC_OK
27 SC_DETECTED
26 SOF_DETECTED
25 TX_RF_STATUS
24 RF_DET_STATUS
23:1 RESERVED
6
15 CLOCK_ERROR
14 BMA_TRANSFER_ONGO
ING
13 TX_READ_ERROR
12 TX_LATENCY_ERROR
11 TX_NO_DATA_ERROR
10:8 RF_ACTIVE_ERROR_CA
USE
7:6 RESERVED
5 RX_ENABLE
4 TX_ACTIVE
UM10858
User manual
COMPANY PUBLIC
Access Value Description
R 0 reserved
R 0*, 1 This bit indicates that the DPLL controller has enabled the DPLL
This bit indicates than the AGC has detected the external RF-
R 0*, 1
Field was switched off while transmitting in SL-ALM mode.
Note: Only valid if the detection mode is enabled with the
register bit-field AGC_RF_DETECT_SEL.
R 0, 1 This bit indicates the status of the actual CRC calculation. If 1
the CRC is correct, meaning the CRC register has the value 0
or the residue value if inverted CRC is used.
Note: This flag should only by evaluated at the end of a
communication
R 0*, 1 Status signal indicating that a subcarrier is detected
R 0*, 1 Status signal indicating that a SOF has been detected
R 0*, 1 If set to 1 this bit indicates that the drivers are turned on,
meaning an RF-Field is created by the device itself
R 0*, 1 If set to 1 this bit indicates that an external RF-Field is detected
by the rf level detectors (after digital filtering)
R 0 reserved
R 0, 1 If set to 1 CLIF is operating on the temporary clock.
R 0, 1 Status signal from Buffer Manager to indicate that a transfer is
actually ongoing.
R 0*, 1
R 0*, 1
R 0*, 1
R 0* - 5
0* No Error; reset value
1 External field was detected on within TIDT timing
2 External field was detected on within TADT timing
3 No external field was detected within TADT timings
4 Peer did switch off RF Field without but no Rx event was raised
(no data received)
5 - 7 Reserved
R 0 Reserved
R 0*, 1 This bit indicates if the RXDecoder is enabled. If 1 the
RXDecoder was enabled by the Transceive Unit and is now
ready for data reception.
R 0*, 1 This bit indicates activity of the TXEncoder. If 1 a transmission
is ongoing, otherwise the TXEncoder is in idle state.
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
157 of 345