NXP Semiconductors PN7462 series User Manual page 133

NXP Semiconductors
Bit Symbol
0 TIMER0_TIMEOUT_SET_ENABLE
Table 171. TIMERS_INT_STATUS_REG (address offset 0x3FE0)
Bit Symbol
31:4 RESERVED
3 TIMER3_TIMEOUT_STATUS
2 TIMER2_TIMEOUT_STATUS
1 TIMER1_TIMEOUT_STATUS
0 TIMER0_TIMEOUT_STATUS
Table 172. TIMERS_INT_ENABLE_REG (address offset 0x3FE4)
Bit Symbol
31:4 RESERVED
3 TIMER3_TIMEOUT_ENABLE
2 TIMER2_TIMEOUT_ENABLE
1 TIMER1_TIMEOUT_ENABLE
0 TIMER0_TIMEOUT_ENABLE
Table 173. TIMERS_INT_CLR_STATUS_REG (address offset 0x3FE8)
Bit Symbol
31:4 RESERVED
3 TIMER3_TIMEOUT_CLR_STATUS
2 TIMER2_TIMEOUT_CLR_STATUS
1 TIMER1_TIMEOUT_CLR_STATUS
0 TIMER0_TIMEOUT_CLR_STATUS
UM10858
User manual
COMPANY PUBLIC
Reset Access Type
Value
0 W
Reset Access Type
Value
0 R
0 R
0 R
0 R
0 R
Reset Access Type
Value
0 R
0 R
0 R
0 R
0 R
Reset Access Type
Value
0 W
0 W
0 W
0 W
0 W
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
Description
0: no effect
1: set enable for Timer0 timeout interrupt
0: no effect
Description
reserved
Timer3 timeout interrupt status
Timer2 timeout interrupt status
Timer1 timeout interrupt status
Timer0 timeout interrupt status
Description
Reserved
Timer3 timeout interrupt enable
Timer2 timeout interrupt enable
Timer1 timeout interrupt enable
Timer0 timeout interrupt enable
Description
reserved
1: clear Timer3 timeout interrupt
0: no effect
1: clear Timer2 timeout interrupt
0: no effect
1: clear Timer1 timeout interrupt
0: no effect
1: clear Timer0 timeout interrupt
0: no effect
© NXP B.V. 2018. All rights reserved.
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