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register TRANSCEIVE_CONTROL_REG in combination with the transmit or the receive
command.
Unlike for normal operation the receiver is enabled again after a reception is finished. It is
necessary to issue the IDLE command in order to leave the RXMultiple cycle. As there is
only one receive buffer available but several responses are expected the buffer is split
into sub buffers of 32-byte length. Hence, the maximum number of responses which can
be handled is limited to 8. As the maximum length defined for a FeliCa response is 20
bytes the buffer size defined does fulfill the requirements for that use-case. The first data
frame received is copied onto buffer address 0. The subsequent frames will be copied to
the buffer address 32 * NumberOfReceivedFrames. The maximum number of data bytes
allowed per frame is limited to 28.
All bytes in the buffer between the payload and the status byte are un-initialized and
therefore invalid. FW has to take care that these bytes are not used. The last word of the
sub buffer (position 28 to 31) contains a status word. The status word contains the
number of received bytes (may vary from the FeliCa length in case of an error), the
CLError flag indicating any error in the reception (which is a combination of 3 individual
error flags DATA_INTEGRITY_ERROR || PROTOCOL_ERROR ||
COLLISION_DETECTED) the individual error flags and the LenError flag indicating an
incorrect length byte (either length byte is greater than 28 or the number of received
bytes is shorter than indicated by the length byte). All unused bits (RESERVED) are
masked to 0.
Fig 29. RXMultiple data format
There are 4 different scenarios possible for reception:
1. Correct reception - Data integrity is correct (no CRC error), and additionally the
2. Erroneous reception - Data is incorrect (data integrity error - CRC wrong) but frame
UM10858
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number of bytes received is equal to the length byte. Data is written to the buffer. No
error set in status byte.
length is correct. Data is written to buffer and the bits CLError and DataError in the
status byte are set.
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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