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NXP Semiconductors
14.2.9.11 SPIM_INT_CLR_ENABLE_REG
This register is a collection of Clear Interrupt Enable commands. Writing 1 to this register
does set the corresponding Interrupt Request ENABLE flag. Writing 0 to this register has
no effect.
Table 305. SPIM_INT_CLR_ENABLE_REG (address offset 0x3FD8)
Bit
31:10
9
8
7:3
2
1
0
14.2.9.12 SPIM_INT_SET_ENABLE_REG
This register is a collection of Set Interrupt Enable commands. Writing 1 to this register
does set the corresponding Interrupt Request ENABLE flag. Writing 0 to this register has
no effect.
Table 306. SPIM_INT_SET_ENABLE_REG (address offset 0x3FDC)
Bit
31:10
9
8
7:3
2
1
0
UM10858
User manual
COMPANY PUBLIC
Symbol
RESERVED
AHB_ADDR_ERROR_CLR_
ENABLE
AHB_ERROR_CLR_ENABLE W
RESERVED
WATERLEVEL_REACHED_
CLR_ENABLE
EOT_CLR_ENABLE
EOR_CLR_ENABLE
Symbol
RESERVED
AHB_ADDR_ERROR_SET_
ENABLE
AHB_ERROR_SET_ENABLE W
RESERVED
WATERLEVEL_REACHED_S
ET_ENABLE
EOT_SET_ENABLE
EOR_SET_ENABLE
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Access Reset
Description
Value
W
0
Reserved
W
0
1 - clear enable for AHB address
overflow interrupt
0
1 - clear enable for AHB Slave error
interrupt
0 - no effect
W
0
Reserved
W
0
1 - clear enable for water level
reached interrupt
0 - no effect
W
0
1 - clear enable for EOT interrupt
0 – no effect
W
0
1 - clear enable for EOR interrupt
0 - no effect
Access Reset
Description
Value
W
0
Reserved
W
0
1 - set enable for AHB address
overflow interrupt
0
1 - set enable for AHB Slave error
interrupt
0 - no effect
W
0
Reserved
W
0
1 - set enable for water level reached
interrupt
0 - no effect
W
0
1 - set enable for EOT interrupt
0 – no effect
W
0
1 - set enable for EOR interrupt
0 - no effect
UM10858
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