NXP Semiconductors PN7462 series User Manual page 245

NXP Semiconductors
14.1.9.12 INT_CLR_ENABLE_REG
This register is a collection of Clear Interrupt Enable commands. Writing 1 to this register
does clear the corresponding Interrupt Request ENABLE flag. Writing 0 to this register
has no effect.
Table 287. INT_CLR_ENABLE_REG (address offset 0x3FD8)
Legend: * reset value; <= mandatory value
Bit Symbol
31:12
RESERVED
11
CLR_ENABLE_TX_FIFO_
THRES
10
CLR_ENABLE_RX_FIFO_
THRES
CLR_ENABLE_FIFO_EM
9
PTY
8 CLR_ENABLE_FIFO_FUL
L
7:4 RESERVED
CLR_ENABLE_I2C_BUS_
3
ERROR
CLR_ENABLE_NACK
2
1 CLR_ENABLE_ARB_FAIL
URE
0 CLR_ENABLE_TRN_COM
PLETED
14.1.9.13 INT_SET_ENABLE_REG
This register is a collection of Set Interrupt Enable commands. Writing 1 to this register
does set the corresponding Interrupt Request ENABLE flag. Writing 0 to this register has
no effect.
Table 288. INT_SET_ENABLE_REG (address offset 0x3FDC)
Legend: * reset value; <= mandatory value
Bit Symbol
31:12 RESERVED
SET_ENABLE_TX_FIFO_
11
THRES
10 SET_ENABLE_RX_FIFO_
THRES
9 SET_ENABLE_FIFO_EMP
TY
8 SET_ENABLE_FIFO_FUL
L
7:4 RESERVED
3 SET_ENABLE_I2C_BUS_
ERROR
UM10858
User manual
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Access Value Description
R 0x0* reserved
W 0x0*
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
W 0x0* Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
W 0x0*
Writing 1 to this register does cl e ar the corresponding IRQ
ENABLE flag
W 0x0*
Writing 1 to this register does cl e ar the corresponding IRQ
ENABLE flag
R 0x0*
reserved
W 0x0*
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
W 0x0*
Writing 1 to this register does cl e ar the corresponding IRQ
ENABLE flag
W 0x0*
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
W 0x0*
Writing 1 to this register does cl e ar the corresponding IRQ
ENABLE flag
Access Value Description
R 0x0* reserved
Writing 1 to this register does set the corresponding IRQ
W 0x0*
ENABLE flag
W 0x0* Writing 1 to this register does set the corresponding IRQ
ENABLE flag
W 0x0* Writing 1 to this register does set the corresponding IRQ
ENABLE flag
W 0x0* Writing 1 to this register does set the corresponding IRQ
ENABLE flag
R 0x0* reserved
W 0x0* Writing 1 to this register does set the corresponding IRQ
ENABLE flag
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Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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