Usb Pll Register Description - NXP Semiconductors PN7462 series User Manual

NXP Semiconductors
Bit Symbol
6 XTAL_VOLTAGE_MUX_CLOC
K
5 XTAL_SEL_EXTERNAL_CLOC
K
4 XTAL_ENABLE
3 XTAL_ENABLE_KICK
2 XTAL_BYPASS
1 XTAL_CONTROL_SW
0 HFO_ENABLE
7.5.1.2 HFO Trimming Value Register
Table 55. CLKGEN_HFO_TRIMM_REG (address 0008h)
Bit Symbol
31:5 RESERVED
4:0 HFO_TRIMM

7.6 USB PLL register description

The USB PLL is controlled by the registers shown in
are ignored.
Warning: Improper setting of USB PLL values may result in incorrect operation of
the USB.
Table 56. USB PLL Registers
Name
CLKGEN_USB_PLL_CONTROL_
REG
CLKGEN_USB_PLL_MDEC_WO_
SOFTDEC_REG
UM10858
User manual
COMPANY PUBLIC
Access Value Description
R/W 0x00
controls XTAL voltage Mux
R/W 0x00 Controls XTAL external clock selection if
XTAL_CONTROL_SW='1'
1: Select External clock
0: Select XTAL Oscillator clock
R/W 0x00 controls XTAL Enable if XTAL_CONTROL_SW='1'
1: Enable for XTAL oscillator
0: Disable XTAL Oscillator
R/W 0x00 Controls XTAL Enable Kick if XTAL_CONTROL_SW='1'
1: Enable Kick of XTAL Oscillator
R/W 0x00 controls XTAL Bypass if XTAL_CONTROL_SW='1'
1: Bypass XTAL
0: XTAL not Bypassed
high to control the XTAL oscillator by SW
R/W 0x00
1: Enable software control of XTAL oscillator
0: Disable software control of XTAL oscillator
R/W 0x01 enables the HFO (activated by default)
1: Enable HFO
0: Disable HFO
Access Value
R/W 0x00
R/W 0x00
Address Width Access
offset (bits)
000Ch 32 R/W
0010h 32 R/W
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Description
Reserved
HFO trimming values
Table 56. Writes to any unused bits
Reset value Description
00F90001h PLL global control register
00000000h PLL M decoded divider ratio
when the soft decoder is not used
UM10858
© NXP B.V. 2018. All rights reserved.
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