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NXP Semiconductors
Bit
Symbol
Table 197. CLIF_TX_FRAME_CONFIG_REG register (address 0038h)
* = reset value
Bit
Symbol
31:19
RESERVED
18:16
TX_DATA_CODE_T
YPE
15:13
TX_STOPBIT_TYPE R/W
12
TX_STARTBIT_ENA
BLE
11
TX_MSB_FIRST
TX_PARITY_LAST_I
10
NV
_ENABLE
9
TX_PARITY_TYPE
8
TX_PARITY_ENABL
E
7:5
RESERVED
UM10858
User manual
COMPANY PUBLIC
Access
Value
101
110
111
Access
Value
R
0
R/W
0*- 7
000b
001b
010b
011b
100b
101-111b
0*- 7
000b
001b
010b
011b
100b
101b
110b
111b
R/W
0*- 1
R/W
0*
R/W
0*
R/W
0*- 1
0
1
R/W
0*- 1
R
0
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Description
212 kHz
424 kHz
848 kHz
Description
Reserved
Specifies the type of encoding of data to be used
No special code
1 out of 4 code [I-Code SLI]
1 out of 256 code [I-Code SLI]
Pulse interval encoding (PIE) [I-Code EPC-V2]
2-bit tuple code (intended only for test purposes)
Reserved
Enables the stop bit (logic "1") and extra guard time (logic
"1"). The value 0 disables transmission of stop-bits.
no stop-bit, no EGT
stop-bit, no EGT
stop-bit + 1 EGT
stop-bit + 2 EGT
stop-bit + 3 EGT
stop-bit + 4 EGT
stop-bit + 5 EGT
stop-bit + 6 EGT
If set to 1, a start-bit (logic "0") will be send
If set to 1, data bytes are interpreted MSB first for data
transmission
If set to 1, the parity bit of last byte (data or crc) is
inverted
Defines the type of the parity bit
Even Parity is calculated
Odd parity is calculated
If set to 1, a parity bit is calculated and appended to each
byte transmitted.
If the Transmission Of Data Is Enabled and
TX_NUM_BYTES_2_SEND is zero, then a
NO_DATA_ERROR occurs.
Reserved
UM10858
© NXP B.V. 2018. All rights reserved.
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