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NXP Semiconductors
Bit
Symbol
2
SYNC_HIGH
1
FSK
0
BPSK
Table 220. CLIF_SIGPRO_ADCBCM_THRESHOLD_REG register (address 00C0h)
* = reset value
Bit
Symbol
31:29
RESERVED
28:16
EDGE_DETECT_TH R/W
15:13
RESERVED
12:0
BIT_DETECT_TH
Table 221. CLIF_AGC_CONFIG0_REG register (address 00CCh)
* = reset value
Bit
Symbol
[1]
31
INTERNAL_USE
30:24
FOR INTERAL
[1]
USE
[1]
23:15
INTERNAL_USE
14:5
AGC_TIME_CONST
ANT
[1]
4
INTERNAL_USE
3
AGC_INPUT_SEL
2
AGC_LOAD
1
AGC_MODE_SEL
0
AGC_MODE_ENABL
E
[1]
Bit-field are either set by HAL or use default value from CLIF EEPROM default settings
UM10858
User manual
COMPANY PUBLIC
Access
Value
R/W
0* - 1
R/W
0*-1
R/W
0*-1
Access
Value
R
0
0000h* -
1FFFFh
R
0
R/W
0000h* -
1FFFFh
Access
Value
R/W
0
R/W
0*-7Fh
R/W
0*-1FFh
R/W
0*-3FFh
R/W
0*, 1
R/W
0*, 1
W
0*, 1
R/W
0*, 1
0*
1
R/W
0*-1
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
PN7462 family HW user manual
Description
Defines if the bit grid is fixed at maximum (1) or at a minimum
(0) value of the correlation.
If set to 1, the demodulation scheme is FSK.
If set to 1, the demodulation scheme is BPSK.
Description
Reserved
Threshold for the edge decision block of the ADCBCM
Reserved
Threshold for the "bit" decision block of the ADCBCM.
Description
For internal use
For internal use
For internal use
Time constant for the AGC update. An AGC period is given
by (AGC_TIME_CONSTANT+1) * 13.56 MHz
For internal use
Selects the AGC value to be loaded into the AGC and the
source for manual mode:
If set, one AGC control value is loaded from
Selects the operation mode of the AGC:
Rx-Divider is controlled by the register
CLIF_AGC_INPUT_REG.AGC_CM_VALUE or
CLIF_AGC_INPUT_REG.AGC_RM_VALUE (Dependent on
AGC_INPUT_SEL).
Rx-Divider value is controlled by the AGC.
If set, the AGC is enabled. If not set, the Rx-Divider is
controlled by either the internal AGC register or a register
value (dependent on AGC_MODE_SEL).
UM10858
© NXP B.V. 2018. All rights reserved.
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