Table of Contents
Advertisement
NXP Semiconductors
Table 324. HOSTIF_CONTROL_REG (address offset 0x0004)
Bit
31:21
20:7
6
5
4
3
2
1
0
[2]
HOSTIF_HEADER_CONTROL_REG
This register is used control the header description.
Table 325. HOSTIF_HEADER_CONTROL_REG (address offset 0x0008)
Bit
31:8
11:10
9:8
7:5
4:3
2:0
UM10858
User manual
COMPANY PUBLIC
Symbol
RESERVED
BUFFERS_SIZE
HIF_ENABLE
NCI_LENGTH_MODE
[2]
NCI_CRC_DISABLE
[2]
NCI_MODE
SHORT_FRAME_LEN
STORE_RX_ERROR_
FRAMES
BUFFER_FORMAT
This bit only has effect if NCI_MODE = 1;
Symbol
RESERVED
HEADER_SIZE
LENGTH_MSB_BYTE
_POS
LENGTH_MSB_BIT_P
OS
LENGTH_LSB_BYTE_
POS
LENGTH_LSB_BIT_P
OS
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
Access
Value
Description
R
0
Reserved
R/W
0x2FFF
RAM aperture size
R/W
0
0- All inputs disabled. Should be
programmed to 1 when host if is fully
configured only. Includes USB.
R/W
0
0 - Length in memory and transferred over
HDLL header
1 - Length in register. Not transferred over
physical interface
R/W
0
0 – CRC active
1 – No CRC
R/W
0
0 – NCI not used
1 – NCI mode active
R/W
0
Maximum number of payload bytes in a
short frame
0 – 2 bytes
1 – 3 bytes
R/W
0
Store erroneous RX frames.
HOSTIF_DATA_READY_STATUS_REG.
RX<n>_DATA_READY is set by Host IF as
if frame were received error-free.
R/W
0
0 - HDLL Frames
1 - Native format
For NCI mode description see chapter 14.3.2.5
Access
Reset
Description
Value
R
0
Reserved
W
1
Number of bytes -1 of header. Default is
for HDLL header.
W
0
Byte position of Length MSB (in reception
order). Default is for HDLL header.
W
1
Bit position of Length MSB. Default is for
HDLL header.
W
1
Byte position of Length LSB (in reception
order). Default is for HDLL header.
W
0
Bit position of Length LSB. Default is for
HDLL header.
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
293 of 345
Advertisement
Table of Contents
