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In the master transmitter mode data is transmitted from master to slave. The first byte
transmitted contains the slave address and Write bit. The data is transmitted 8 bits at a
time. After each byte is transmitted, an acknowledge bit is received. The I2C Master in
Master Transmitter mode supports the automatic continuation of the I2C transmission
without the need of altering the data in the FIFO or the register content. The Stop
condition is generated when the byte sent is equal to the content of the byte count
register. In case of error during the ongoing communication, the FIFO has to be cleared
(corresponding register to clear FIFO based on interrupt error). When the FIFO is empty
during the transmission, the block will automatically stretch the clock of the previous byte
(after slave acknowledge) until a new byte is written.
The transfer in the master receiver mode is initiated in the same way as in the master
transmitter mode. The number of bytes to receive must be specified in the byte count
register. The I2C slave can always stretch the clock if it is not able to transmit any more
data. The Stop condition is generated when the number of bytes received is equal to the
byte count register content. When the FIFO is full, the clock is stretched before sending
the bit acknowledge to the slave. An interrupt will be raised to indicate that some FIFO
data need to be fetched.
14.1.3 Pin description
Table 274. I²C-bus pin description
Pin Name
SDA
SCL
UM10858
User manual
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
Pin description
I²C Serial Data
I²C Serial Clock
© NXP B.V. 2018. All rights reserved.
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