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NXP Semiconductors
Bit
Symbol
[1]
Bit-field are either set by HAL or use default value from CLIF EEPROM default settings
Table 234. CLIF_ANA_TX_SHAPE_CONTROL_REG register (address 0128h)
* = reset value
Bit
Symbol
31:29
RESERVED
28:24
TX_RESIDUAL_CARRIER_O
V_ PREV
23:18
RESERVED
17
TX
_SET_BYPASS_SC_SHAPIN
G
RESERVED
16:12
TX_SET_SLEW_SHUNTREG
11:8
TX_SET_TAU_MOD_FALLIN
7:4
G
TX_SET_TAU_MOD_RISIN
3:0
G
Table 235. CLIF_ANA_TEST_REG register (address 01FCh)
* = reset value
Bit
Symbol
31:27
RESERVED
26
RESERVED
25
RESERVED
24
RESERVED
UM10858
User manual
COMPANY PUBLIC
Access
Value
Description
Note that the phase settings can be refined (on top of
this configuration) in 5°C steps using
CLIF_DPLL_INIT_REG.
DPLL_CLOCK_CONFIG_ALM.
0*
0 °C
1
45 °C
2
90 °C
3
135 °C
4
180 °C
5
225 °C
6
270 °C
7
315 °C
Access
Value
Description
R
0
Reserved
R/W
0* - 1Fh
Defines the value for the residual carrier for the period the
overshoot prevention pattern is active.
R
0
Reserved
R/W
0*, 1
Bypasses switched capacitor shaping of the Transmitter
Signal
R
0
Reserved
R/W
0h*-Fh
Set slew rate for shunt regulator
R/W
0h*-Fh
Transmitter TAU setting for falling edge of modulation
shape. In AnalogControl module the output signal is
switched with the tx_envelope.
Only valid is TX_SET_BYPASS_SC_SHAPING is set
R/W
0h*-Fh
Transmitter TAU setting for rising edge of modulation
shape. In AnalogControl module the output signal is
switched with the tx_envelope.
Only valid is TX_SET_BYPASS_SC_SHAPING is set
Access
Value
Description
R
0*
Reserved
R/W
0*, 1
Reserved
R/W
0*, 1
Reserved
R/W
0*, 1
Reserved
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
185 of 345
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