NXP Semiconductors PN7462 series User Manual page 231

NXP Semiconductors
Remark: When both bits EARLY and MUTE are high, it means that the card answered
(sent its ATR) too early between 200 CLK periods after I/O line goes high and before
RST goes high.
13.6.2.24 Register ct_usr2_reg (UART Status Register 2)
This register is an interrupt register (together with ct_usr1_reg register): these bits
coming from the Contact UART core are used to manage the reception & transmission of
characters. Read this register enables to know what the cause of the interrupt is. The bits
are set to logic 1 by hardware and set to logic 0 by reading (with a hardware mechanism
avoiding the loss of incoming interrupt while reading).
Table 273. ct_usr2_reg (address 0068h) bit description
Bit Symbol Access
31:8 RESERVED -
7 to3 R
6 to2 R
5 to1 R
4 wrdaccerr R
3 INTAUXL R
2 PROTL R
1 PRESL R
0 PTL R
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Reset
Description
Value
0 Reserved
0b Time Out counter3:
Set to logic 1 when the timer counter 3 has reached its terminal count.
Set to logic 0 after reading the byte.
0b Time Out counter2:
Set to logic 1 when the timer counter 2 has reached its terminal count.
Set to logic 0 after reading the byte.
0b Time Out counter1:
Set to logic 1 when the timer counter 1 has reached its terminal count.
Set to logic 0 after reading the byte.
0b WoRD ACCess ERRor:
Set to logic 1 if a word (bit wrdacc = 1 in register
ct_ucr21_reg/ct_ucr22_reg) read access is attempted with less than 4 bytes
present into the FIFO.
Set to logic 0 after reading the byte.
0b AUXiliary INTerrupt Latched:
Set to logic 1 if the level on pin INTAUX has been changed.
Set to logic 0 after reading the byte.
0b PROTection Latched:
Set to logic 1 when an overload occurs.
Set to logic 0 after reading the byte.
0b PRESence Latched:
Set to logic 1 when the card has been inserted or extracted.
Set to logic 0 after reading the byte.
Remark: the bits pres_pup_en and pres_con_no in ct_ssr_reg register
should have been set prior to any check of card presence.
0b Protection Temperature Latched:
Set to logic 1 when an overheating occurs.
Set to logic 0 after reading the byte.
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
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PN7462 family HW user manual
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