NXP Semiconductors PN7462 series User Manual page 270

NXP Semiconductors
14.3.2 SPI Slave interface
The host interface of PN7462 family can be also used as SPI slave interface. The SPI
slave controller is the second of the two SPI controllers supported by PN7462 family. For
more details on the I2C master controller please refer to
14.3.2.1 SPI Slave features
14.3.2.2 SPI Slave pin description
Table 314. SPI pinning
Pin Number
6
7
8
9
14.3.2.3 Configuring the SPI interface
The following parameters can be configured via the register
HOSTIF_SPI_CONTROL_REG:
• SPI_CPOL: polarity of SPI clock
• SPI_CPHA: phase of SPIO clock
The Host Interface Core ensures that changes to these parameters will not take effect
while the interface core is BUSY (logic high).
14.3.2.4 HDLL Mode
The HDLL mode requires a transfer direction detector, because only half duplex is
supported. For this reason, the first byte is evaluated. If the first bit of the first byte is logic
low (SOF true), the SPI frame is treated as a Host Write. The Host Interface transmits
FFh on MISO. If this bit and all other bits in the byte are logic high, the SPI frame is
UM10858
User manual
COMPANY PUBLIC
•
Speed up to 7 Mbit/s
•
Slave mode only
•
8-bit data format only
•
Programmable clock polarity and phase
•
Slave selection fixed to positive polarity
•
Supports all 4 modes of SPI (CPOL and CPHA)
•
Half duplex in HDLL Mode
•
Full duplex mode in native mode
Pin Name
ATX_A
ATX_B
ATX_C
ATX_D
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
SPI slave Description
NSS SPI active-low Slave Select (NSS)
SPI Master Output Slave Input
MOSI
(MOSI)
MISO SPI Master Input Slave Output
(MISO)
SCK SPI Serial clock (SCK)
314514
UM10858
PN7462 family HW user manual
Section 14.2.
© NXP B.V. 2018. All rights reserved.
270 of 345