NXP Semiconductors PN7462 series User Manual page 69

NXP Semiconductors
Bit Symbol
1 CLIF_PLL_FUNC_TEST2_LOCK2
0 CLIF_PLL_FUNC_TEST1_LOCK2
7.7.3 CLIF PLL GLOBAL CONTROL REG
The CLIF PLL GLOBAL CONTROL REG register contains the bits that enable and
connect CLIF PLL. Enabling CLIF PLL allows it to attempt to lock to the current settings
of the multiplier and divider values.
Table 63. CLKGEN_CLIF_PLL_GLOBAL_CONTROL_REG (address 0020h)
Bit Symbol
31:15 RESERVED
14 CLIF_PLL_CLK_IN_OK_BYPASS
13:12 CLIF_PLL_REF_CLK_SELECT
11 RESERVED
10 CLIF_CLK_DETECT_ENABLE
9:7 CLIF_PLL_INPUT_FREQ_SEL
6:5 CLIF_PLL_CLOCK_SELECT
4 PLL_INPUT_BUFFER_BYPASS
3 PLL_INPUT_BUFFER_ENABLE
2 CLIF_PLL_FUNC_TEST_N1
1 CLIF_PLL_DIVN1
0 CLIF_PLL_ENABLE
UM10858
User manual
COMPANY PUBLIC
Access Value Description
1: Bypass clif_pll_lock2
R/W 0x00 1: Enable functional CLIF_PLL test chain of lock detector
2
R/W 0x00 1: Enable functional divider test of lock detector 2
Access Value Description
R/W 0x00 Reserved
R/W 0x00 CLIF PLL clk_in detection override
1: Override pll_clk_in detection
R/W 0x00 Select the reference clock for CLIF PLL
00: Clk_input_buffer
01: clk_xtal
10: tie '0'
11: tie '0'
R/W 0x00 Reserved
R/W 0x00 1: Enable CLIF_PLL input clock detector (clk_in).
Higher prior than xtal_detect_enable.
R/W 0x01 Select input frequency for the CLIF_PLL: 13, 19.2, 24,
26, 38.4 or 52 MHz
R/W 0x02 Selects output clock from CLIF_PLL
00: CLIF_PLL clockout2
01: clk_xtal
10: CLIF_PLL clockout
11: CLIF_PLL input clock
R/W 0x00 Bypass PLL input buffer (the buffer for clock going into
USB PLL and intPLL)
1: Bypass the PLL input buffer
1: Enable the PLL Input Buffer (the buffer for clock
R/W 0x01
going into USB PLL and intPLL)
0: Disable the PLL input Buffer
R/W 0x00 1: Enable functional divider test and CLIF_PLL test
chain of divider M1
0: Disable functional divider test and CLIF_PLL test
chain of divider M1
Pre-divider selection for CLIF PLL1
R/W 0x00
R/W 0x00 1: Enable the CLIF_PLL
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
314514
UM10858
PN7462 family HW user manual
© NXP B.V. 2018. All rights reserved.
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