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NXP Semiconductors
HOSTIF_INT_CLR_STATUS_REG. An EOR event is not generated. The EOR_STATUS
flag in register HOSTIF_INT_STATUS_REG maintains logic low.
Note that there is no RX Frame Overflow detection in native mode.
Note that extra bytes received before the expected CRC bytes will result in a CRC error
and not a RX frame overflow error.
14.3.4.11 RX buffer overflow
If the number of bytes received exceeds the maximum size of the buffer (defined in
HOSTIF_BUFFER_RX<n>_CFG_REG.RX<n>_MAX_SIZE) then the Buffer Manager will
set RX_BUFFER_OVERFLOW_STATUS in register HOSTIF_INT_STATUS_REG and
assert the corresponding output. In the Native Mode, if the number of bytes received
exceeds (MAX_SIZE - 4) where MAX_SIZE is defined in
HOSTIF_BUFFER_RX<n>_CFG_REG.RX<n>_MAX_SIZE, then the Buffer Manager will
set RX_BUFFER_OVERFLOW_STATUS in HOSTIF_INT_STATUS_REG register and
assert the corresponding output to the Host Interface Core. Note that the threshold is
(MAX_SIZE - 4) because the first word in the buffer is reserved for storing the number of
bytes received. The output will remain high until the firmware sets
RX_BUFFER_OVERFLOW_CLR_STATUS in register
HOSTIF_INT_CLR_STATUS_REG. An EOR event is not generated. The EOR_STATUS
flag in register HOSTIF_INT_STATUS_REG maintains logic low. The frame is discarded
by not setting HOSTIF_DATA_READY_STATUS_REG.RX<n>_DATA_READY.
14.3.4.12
CRC verification and generation
The 2-byte data-link CRC is appended to the end of the data-link frame as shown in and
is described by the CRC-16-CCITT polynomial:
This is implemented using the polynomial (1)1021, operating on the bit sequence MSB
first. It has an initial value of 0xFFFF and is calculated over the entire data-link frame
(header and payload). For received frames from the Host Interface Core, the Buffer
Manager continually calculates the CRC. At the end of the frame, it extracts the sent
CRC and compares it with its internally calculated CRC. If there is a mismatch, the Buffer
Manager sets CRC_NOK_STATUS in register HOSTIF_INT_STATUS_REG. The frame
is discarded by not setting
HOSTIF_DATA_READY_STATUS_REG.RX<n>_DATA_READY.
An EOR event is not generated. The EOR_STATUS flag in register
HOSTIF_INT_STATUS_REG maintains logic low.
For transmitted frames, the buffer manager calculates the 2-byte CRC and appends it to
the end of the frame.
Note that there is no CRC in native mode.
UM10858
User manual
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All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
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PN7462 family HW user manual
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UM10858
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