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NXP Semiconductors
Name
SPIM_CRC_STATUS_REG
SPIM_WATERLEVEL_REG
INTERNAL_USE
INTERNAL_USE
SPIM_BUFFER_MAPPING_REG RAM
SPIM_INT_CLR_ENABLE_REG
SPIM_INT_SET_ENABLE_REG
SPIM_INT_STATUS_REG
SPIM_INT_ENABLE_REG
SPIM_INT_CLR_STATUS_REG
SPIM_INT_SET_STATUS_REG
[1]
14.2.9 Register description
14.2.9.1 SPIM_STATUS_REG
This register reflects the current status of the SPI master.
Table 295. SPIM_STATUS_REG (address offset 0000h) bit description
Bit
31:2
1
0
14.2.9.2 SPIM_CONFIG_REG
This register is used to configure the SPI Master.
Table 296. SPIM_CONFIG_REG (address offset 0004h) bit description
Bit
31:19
18:16
15:9
8
UM10858
User manual
COMPANY PUBLIC
Address
offset
001Ch
0020h
0024h
0028h
002Ch
3FD8h
3FDCh
3FE0h
3FE4h
3FE8h
3FECh
The reserved address 0x30 is mapped to a spare register (8 bits). The value read from this location is
0x000000F0. Bits 7:4 are read-write; bits 3:0 are read-only.
Symbol
Access
RESERVED
R
TX_ONGOING
R
RX_ONGOING
R
Symbol
RESERVED
[1]
BAUDRATE
RESERVED
[1]
SLAVE_SELECT
All information provided in this document is subject to legal disclaimers.
Rev. 1.4 — 14 May 2018
Width
Access
Reset value
(bits)
32
R
0000FFFFh
32
R/W
00000000h
32
R/W
00000000h
32
R
00000000h
32
R/W
00002FFFh
32
W
00000000h
32
W
00000000h
32
R
00000000h
32
R
00000000h
32
W
00000000h
32
W
00000000h
Reset
Description
Value
0
Reserved
0
1 - TX buffer is currently in use by the
hardware. Any TX_START/RX_START
command will be ignored while
TX_ONGOING=1
0
1 - RX buffer is currently in use by the
hardware. Any TX_START/RX_START
command will be ignored while
RX_ONGOING=1
Access
Reset
Description
Value
R
0
Reserved
R/W
0
SCK frequency (Baudrate) Selection
R
0
Reserved
R/W
0
1: Slave 1 is selected (Pin: GPIO1)
0: Slave 0 is selected (Pin: SPIM_SSN).
314514
UM10858
PN7462 family HW user manual
Description
RX/TX CRC values
Water level
For internal use
For internal use
Buffer Mapping
Clear interrupt enable
Set interrupt enable
Interrupt status
Interrupt enable
Clear interrupt
Set interrupt
© NXP B.V. 2018. All rights reserved.
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