NXP Semiconductors PN7462 series User Manual page 281

NXP Semiconductors
HDLL CRC) and checks for frame over/underflow and inter-character timeout. For
outgoing frames, the buffer manager monitors the delay between bytes. Exceeding a
threshold will trigger an interrupt. It supports up to 4 receive buffers and 1 transmit buffer
listed in
Table 319. Buffer ID assignment
Buffer Name
RX0
RX1
RX2
RX3
TX
The buffer manager supports various transport streams (HDLL, native, NCI) which are not
supported equally for each interface (depending on physical/logical difference in
protocols).
Table 320. ed format per interface
Interface
I2C
SPI
HSU
14.3.4.1 Buffer initialization
RX buffers
Each of the RX buffers may be independently disabled by setting bit
RX<n>_BUFFER_DISABLE logic high in register HOSTIF_BUFFER_RX<n>_CFG_REG.
Each of the RX buffers must be configured with the following parameters, which are
defined in HOSTIF_BUFFER_RX<n>_CFG_REG:
• Maximum buffer size
• Start address
• Normal or short frame assignment
• Header offset
The maximum buffer size should be set to be greater than or equal to the sum of:
• HOSTIF_BUFFER_RX<n>_CFG_REG.RX<n>_HEADER_OFFSET
• Number of header bytes
• Payload
It is used to detect an RX buffer overflow (described in
The start address is defined in field
UM10858
User manual
COMPANY PUBLIC
Table 319.
HDLL Native
(debug
only)
Yes Yes
Yes Yes
Yes Yes
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Rev. 1.4 — 14 May 2018
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PN7462 family HW user manual
Buffer ID
0
1
2
3
4
NCU, NCI,
No Header, No Header, Header,
No CRC CRC
Yes Yes
Yes Yes
Yes Yes
Section
UM10858
NCI, NCI,
Header,
No CRC CRC
Yes Yes
Yes Yes
Yes Yes
14.3.4.11).
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